This invention relates to digital phase lock loop decoders and more particularly to the decoding of Manchester coded data. In Manchester coded data a signal transition is present at each mid-cell location, the direction of the transition representing the value of the encoded binary bit.
A digital phase lock loop decoder for decoding Manchester coded data is known from U.S. Pat. No. 4,584,695. This known decoder employs a multiphase driver clock circuit which provides clock signals which are phase-offset from one another. One clock output signal is used as the driver clock to provide a sample clock signal at four times the data rate or, in a fast clock mode, at eight times the data rate to determine whether the PLL reference clock is leading or lagging with respect to the received data signal. Thus, the known decoder has the disadvantage of needing relatively high rate clock signals, thereby rendering unsuitable the utilization of relatively lower speed, low cost implementation technologies, such as CMOS.